Digital integrated circuits constructed according to conventional Built In Self Test (BIST) architectures comprise dedicated test circuitry in addition to operational circuitry required to perform functions expected of the integrated circuits in their intended applications. The dedicated test circuitry normally includes test pattern generators for generating test patterns, test response compactors for compressing results of test pattern application to the operational circuitry, and multiplexors used to switch between normal operating configurations and test configurations. The dedicated test circuitry can add a substantial hardware overhead, and introduction of the multiplexors into signal paths used during normal operation of the integrated circuits can degrade normal operation of the integrated circuits.
Some functional blocks of integrated circuits are difficult to test even using BIST techniques. For example, digital integrators of digital decimators used to band limit Sigma Delta Modulation (SDM) signals are difficult to test because digital words applied to the decimators are limited to only two possible differential values. A test pattern comprising only such digital words must be very long to ensure that the probability of making internal faults of the digital integrator observable is high enough for practical applications.